1. Field of the Invention
Embodiments of the invention relate to a method of fabricating a flash memory device, and more particularly, to a method of fabricating a flash memory device using a process for forming a self-aligned floating gate.
2. Description of the Related Art
Flash memory is nonvolatile, generally has excellent data integrity, and can have high integration density like dynamic random access memory (DRAM). Because flash memory has the characteristics described above, it may be used, for example, for the main memory in a computer system. Additionally, flash memory is a suitable replacement for hard disks and floppy disks because flash memory generally has high integration density and large storage capacity.
A cell transistor in a flash memory device is generally a stacked gate transistor comprising a gate structure in which a tunnel oxide layer, a floating gate, an inter-gate insulating layer, and a control gate are stacked. The program operation for a flash memory device comprising the stacked gate structure described above generally involves the application of a positive voltage to the control gate. During the program operation, the positive voltage that is applied to the control gate is coupled with the floating gate and electrons in a substrate are then captured in the floating gate when electrons move from the substrate through the tunnel oxide layer and into the floating gate through Fowler-Nordheim tunneling and hot carrier injection. A relatively high coupling ratio between the control gate and the floating gate is required in order to apply a relatively strong electric field to the tunnel oxide layer while applying a relatively low input voltage to the control gate. The coupling ratio, as used herein, is a ratio of the voltage induced at the floating gate to the voltage applied to the control gate. The coupling ratio is also represented as a ratio of the capacitance of the inter-gate insulating layer to the total capacitance of the tunnel oxide layer and the inter-gate insulating layer.
Figure (FIG.) 1 is a schematic cross-sectional view of a cell transistor of a conventional flash memory device.
Referring to FIG. 1, an isolation layer 2 is formed in a substrate 1 to define active regions. A floating gate 4 is formed on an active region, and a tunnel oxide layer 3 interposed between floating gate 4 and substrate 1. A control gate 7 is formed on floating gate 4, and an inter-gate insulating layer 6 is interposed between control gate 7 and floating gate 4.
In the flash memory device of FIG. 1, the coupling ratio is affected by the surface area of the portion of inter-gate insulating layer 6 that is formed on an upper surface and both sidewalls of floating gate 4. Accordingly, the size of floating gate 4 must be increased in order to increase the surface area of the portion of inter-gate insulating layer 6 formed on floating gate 4 to thereby increase the coupling ratio of the flash memory device of FIG. 1.
As the critical dimensions (e.g., line width) of flash memory devices decrease, properly aligning floating gate 4 with the active region when forming floating gate 4 becomes particularly important. In a method for manufacturing a cell transistor of the flash memory device illustrated in FIG. 1, isolation layer 2 is formed in substrate 1 to define active regions of substrate 1. Thereafter, a polysilicon layer is deposited on the entire surface of substrate 1, and the polysilicon layer is then patterned to form floating gate 4 on an active region of substrate 1. However, as the critical dimensions for the active region and floating gate 4 decrease, the active region and floating gate 4 are often misaligned when floating gate 4 is formed through a photolithography process. This misalignment degrades the distribution of an erase threshold voltage Vth.
A method for forming a self-aligned floating gate, which is illustrated in FIGS. 2 through 5, has been proposed in response to the misalignment problem described above.
Referring to FIG. 2, mask patterns 15 for defining active regions of substrate 10 are formed on substrate 10 and trenches 25 are formed in substrate 10 using mask patterns 15. Thereafter, an insulating layer is deposited to fill trenches 25 and the spaces between mask patterns 15. The insulating layer is then planarized to form isolation layers 30. Referring to FIG. 3, mask patterns 15 are then removed and, as a result, upper portions of isolation layers 30 protrude from a surface of substrate 10 and define holes H. Holes H are formed in the areas from which mask patterns 15 have been removed, and floating gates will subsequently be formed in holes H. Referring to FIG. 4, sidewalls of isolation layers 30 are etched (i.e., pulled back) through wet etching process to expand the width of each hole H. When sidewalls of isolation layers 30 are etched, the resulting surface area of the floating gates to be formed in holes H, and thus the coupling ratio of the flash memory device, increases relative to the floating gates formed when the sidewalls of isolation layers 30 are not etched. Referring to FIG. 5, a tunnel oxide layer 35 is then formed on substrate 10 between adjacent isolation layers 30, and polysilicon is then deposited on tunnel oxide layer 35 to fill holes H. Thereafter, a planarization process is performed using chemical mechanical polishing (CMP) to form self-aligned floating gates 40 disposed between adjacent isolation layers 30. Then, although it is not illustrated in FIG. 5, isolation layers 30 disposed between self-aligned floating gates 40 are etched (i.e., recessed) through a wet etchback process to expose the sidewalls of self-aligned floating gates 40, thereby increasing the surface area of the portion an inter-gate insulating layer that will be formed on the upper surface and the sidewalls of each self-aligned floating gate 40.
The conventional method described above makes it possible to form a floating gate while substantially preventing misalignment between the floating gate and the active region and efficiently using the area of the active region. However, when the design rule for the flash memory device is reduced to 60 nm to reduce a distance between adjacent cells to 40 nm or less, trenches 25 will not be completely filled with the insulating layer and thus a void V is formed and remains in an isolation layer 30, as illustrated in FIG. 2. Additionally, during the formation of the floating gate, void V is filled with the material used to form the floating gate, so void V will cause an electrical short.
Alternatively, as illustrated in FIG. 6, trenches 25 are filled with an undoped silicate glass (USG) oxide layer 30, which has an excellent inter-layer filling characteristic(s), and then USG oxide layer 30, in which a void is formed, is etched to remove the void from the isolation layer. Thereafter, a hard oxide layer 32, which is harder than USG oxide layer 30, is formed on USG oxide layer 30 in the spaces between mask patterns 15. During the subsequent CMP process, hard oxide layer 32, which is well-suited for isolating nodes (i.e., conducive to node isolation), acts as a planarization stop layer.
Even when double oxide layers 30, 32 (i.e., USG oxide layers 30 and hard oxide layers 32) are formed, it is still necessary to remove mask patterns 15 and reduce the width of (i.e., pull back) isolation layers 30, 32 (i.e., double oxide layers 30, 32) to expand the holes in which floating gates will subsequently be formed, as illustrated in FIGS. 7 and 8.
However, when using isolation layers 30, 32 it is difficult to reduce the widths of isolation layers 30, 32 through a wet etching process because hard oxide layers 32 are relatively highly cohesive to USG layers 30 and have relatively low reactivity to wet chemical etchant; and thus, isolation layers 30, 32 are difficult to etch through a wet etching process. Also, when isolation layers 30, 32 are etched too much (i.e., over-etched) it is difficult to obtain uniformity among the structures formed on a wafer.
In relatively extreme circumstances, etching isolation layers 30, 32 too much may generate a pit P where an active region of substrate 10 and an isolation layer 30, 32 (i.e., USG oxide layer 30) generally meet, as illustrated in FIG. 8. When the wet etching process is not performed in a way that substantially prevents the creation of a pit P, it is difficult to form a flash memory device, using isolation layers 30, 32, that both operates reliably and has an increased coupling ratio relative to when isolation layers 30, 32 are not etched to increase the width of a hole in which a floating gate will be formed.